In such a system, the central unit includes a processor which handles incoming and outgoing data to be written in or read out from an associated data store, e.g. as described in U.S. Pat. No. 3,533,082. The processor receives instructions from a programmer in respective subphases of any phase, these instructions forming part of what may be termed a macroprogram individual to each peripheral unit. Certain instructions within any macroprogram may call for the execution of a predetermined sequence of ancillary instructions, such sequence constituting a subroutine or microprogram. Thus, for example, a macroinstruction "read data store" may initiate a sequence of microinstructions for extracting an address code from a memory, feeding that code to an address input of the data store, activating this store to read out the data word identified by that address, and loading the data word into a register.
In conventional systems operating in the time-division mode (TDM), the number of subphases -- established by a train of clock pulses from a time base -- is the same for all the phases and is so chosen as to allow the maximum number of possible steps of a macroprogram to be carried out during the time when the central unit dialogues with a peripheral unit in its assigned phase. Since in most instances the number of program steps actually carried out during a phase will fall short of this maximum, the average time utilized for executing instructions will be only a fraction of the duration of a phase. Thus, the processor will be idle during a substantial portion of a scanning cycle.
Situations arise, furthermore, in which additional time is required for communication with a particular unit, as when a routinely performed parity check reveals an error and tests are required to determine its source.